Methods and systems of enabling concurrent editing of hierarchical electronic circuit layouts
US10922469B1 · kind B1 · utility
2Cited by
34References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide a new layout editor tool allowing designers to concurrently edit various aspects of an electronic circuit layout, even at disparate hierarchical levels of the design. The new layout editor tool enables multiple electronic circuit designers to concurrently edit a layout a different hierarchical levels, by logically establishing editable child sub cell-level partitions within a parent layout-level partition, each of which representing various components of the same electronic circuit layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.