Data signal delay circuit, delay method and display device
US10923065B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data signal delay circuit and delay method and a display device are disclosed. The data signal delay circuit includes a feedback signal generation sub-circuit, a compensation signal generation sub-circuit, and a control sub-circuit. The feedback signal generation sub-circuit is configured to generate a feedback signal based on a first level signal from the first level signal terminal and a second level signal from the second level signal terminal under the control of a gate drive signal from a scan signal line currently being scanned. The compensation signal generation sub-circuit is configured to generate a compensation signal based on the feedback signal and a data enable signal from the data enable signal line. The control sub-circuit is configured to delay a data enable signal of the data enable signal line in a next cycle based on the compensation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.