Method and apparatus for compensating for high thermal expansion coefficient mismatch of a stacked device
US10923286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2018 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device that incorporates teachings of the subject disclosure may include, for example, a multilayer initial oxide on a silicon substrate, where the multilayer initial oxide comprises amorphous polysilicates and a group one metal or a group two metal; a first electrode layer on the multilayer initial oxide; a dielectric layer on the first electrode layer; a second electrode layer on the dielectric layer, where an edge alignment spacing between at least one pair of corresponding electrode edges of two electrode layers of the capacitor is two microns or less; and connections for the first and second electrode layers. Other embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.