Detecting defects in a logic region on a wafer
US10923317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2223/611
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.