Method of manufacturing a semiconductor device with epitaxial layers and an alignment mark
US10923432B2 · kind B2 · utility
1Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2020 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Feb 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer includes an alignment mark contained within in a kerf region of the semiconductor wafer. The alignment mark includes a groove vertically extending from a main surface of the semiconductor wafer to a bottom surface of the groove, and at least one tin protruding from the bottom surface of the groove. The groove has a rectangular shape with four sidewalls and four inside corners, with each of the four inside corners facing the at least one fin. A minimum distance between the at least one fin and a nearest one of the four inside corners is at least 25 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.