Semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes
US10923503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2018 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/15
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate comprising a trap-rich layer with small grain sizes, as well as the resulting SOI substrate. In some embodiments, an amorphous silicon layer is deposited on a high-resistivity substrate. A rapid thermal anneal (RTA) is performed to crystallize the amorphous silicon layer into a trap-rich layer of polysilicon in which a majority of grains are equiaxed. An insulating layer is formed over the trap-rich layer. A device layer is formed over the insulating layer and comprises a semiconductor material. Equiaxed grains are smaller than other grains (e.g., columnar grains). Since a majority of grains in the trap-rich layer are equiaxed, the trap-rich layer has a high grain boundary area and a high density of carrier traps. The high density of carrier traps may, for example, reduce the effects of parasitic surface conduction (PSC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.