Methods to reduce or prevent strain relaxation on PFET devices and corresponding novel IC products

US10923594B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Dirk Utess · Dresden, DE
• Peter Steinmann · Durham, US
• Stephanie Wilhelm · Dresden, DE

Key dates

• Filing date: Dec 20, 2018
• Grant date: Feb 16, 2021
• Expiry date: Sep 5, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.