Dirk Utess
5Patents
1h-index
9Co-inventors
40Inventor score
Filing activity: Feb 3, 2011 → Mar 28, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8598579B2 | Test structure for ILD void testing and contact resistance measurement in a semiconductor device | Electricity | 18 | Active |
| US9147618B2 | Method for detecting defects in a diffusion barrier layer | Electricity | 1 | Active |
| US10923594B2 | Methods to reduce or prevent strain relaxation on PFET devices and corresponding novel IC products | Electricity | 0 | Active |
| US12324213B2 | Stress layout optimization for device performance | Electricity | 0 | Active |
| US11664432B2 | Stress layout optimization for device performance | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.