Camouflaged FinFET and method for producing same
US10923596B2 · kind B2 · utility
0Cited by
47References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.