Method for reduction of interfacial stress accumulation between double side copper-plated layers and aluminum nitride substrate
US10923621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Oct 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/034
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention uses a photolithography process and an electroplating process to perform. TAV copper filling and patterning of the fabrication of the double side copper-plated layers to plate the double side copper-plated layers in advance at the TAV through holes to serve as a stress buffer layer of the aluminum nitride substrates. Then the subsequent pattern designs of the copper-plated layers are customized. According to the simulation theory calculations, it is proved that the stress which accumulates on the short-side of the copper-plated layer of the aluminum nitride substrate with the asymmetric structure may be effectively reduced to facilitate the improvement of the reliability of the aluminum nitride substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.