Semiconductor testing apparatus
US10928422B2 · kind B2 · utility
1Cited by
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3Claims
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Assignee
Inventor
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/07357
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Provided is a semiconductor testing apparatus that a testing pin is rendered to electrically connect to another testing pin or an external substrate through a conductive layer formed in the guide hole, so that it results in enhancement in various characteristics such as poor electrical contact of the testing pin, space efficiency, noise, and high frequency characteristics, thereby improving reliability in testing results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.