Environmental modification testing for design correctness with formal verification
US10929584B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.