Architecture for table-based mathematical operations for inference acceleration in machine learning
US10929760B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | May 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing unit to support inference acceleration for machine learning (ML) comprises an inline post processing unit configured to accept and maintain one or more lookup tables for performing each of one or more non-linear mathematical operations. The inline post processing unit is further configured to accept data from a set of registers maintaining output from a processing block instead of streaming the data from an on-chip memory (OCM), perform the one or more non-linear mathematical operations on elements of the data from the processing block via their corresponding lookup tables, and stream post processing result of the one or more non-linear mathematical operations back to the OCM after the one or more non-linear mathematical operations are complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.