Ulf Hanebutte
41Patents
5h-index
38Co-inventors
69Inventor score
Filing activity: Feb 27, 2004 → Jul 26, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10896045B2 | Architecture for dense operations in machine learning inference engine | Physics | 32 | Active |
| US7594073B2 | Method and apparatus for caching memory content on a computing system to facilitate instant-on resuming from a hibernation state | Emerging Cross-Sectional Technologies | 16 | Active |
| US7383137B2 | Method and apparatus for measuring absolute and net power consumption for computer systems | Physics | 15 | Expired |
| US12112174B2 | Streaming engine for machine learning architecture | Physics | 7 | Active |
| US8412479B2 | Memory power estimation by means of calibrated weights and activity counters | Physics | 5 | Active |
| US8046559B2 | Memory rank burst scheduling | Emerging Cross-Sectional Technologies | 5 | Active |
| US8438410B2 | Memory power management via dynamic memory operation states | Emerging Cross-Sectional Technologies | 5 | Active |
| US8327172B2 | Adaptive memory frequency scaling | Emerging Cross-Sectional Technologies | 5 | Active |
| US7774520B2 | Method and apparatus for maintaining synchronization of audio in a computing system | Physics | 3 | Active |
| US10079507B2 | Techniques for adaptive demand/response energy management of electronic systems | Emerging Cross-Sectional Technologies | 2 | Active |
| US8738937B2 | Method and apparatus to limit memory power | Emerging Cross-Sectional Technologies | 2 | Active |
| US11977475B1 | Method and apparatus for compiler and low-level instruction validation of machine learning operations on hardware | Physics | 2 | Active |
| US10997510B1 | Architecture to support tanh and sigmoid operations for inference acceleration in machine learning | Physics | 1 | Active |
| US10929760B1 | Architecture for table-based mathematical operations for inference acceleration in machine learning | Physics | 1 | Active |
| US12190086B1 | Method and apparatus for ML graphs by a compiler | Physics | 1 | Active |
| US10824433B2 | Array-based inference engine for machine learning | Physics | 1 | Active |
| US12430108B2 | Multistage compiler architecture | Physics | 0 | Active |
| US10200310B2 | Fabric-integrated data pulling engine | Physics | 0 | Active |
| US12174727B1 | Method and apparatus for correlating high-level code with low-level instructions for machine learning applications | Physics | 0 | Active |
| US11029963B2 | Architecture for irregular operations in machine learning inference engine | Physics | 0 | Active |
| US12112175B1 | Method and apparatus for performing machine learning operations in parallel on machine learning hardware | Physics | 0 | Active |
| US11966857B2 | Architecture to support tanh and sigmoid operations for inference acceleration in machine learning | General | 0 | Revoked |
| US11995448B1 | Method and apparatus for performing machine learning operations in parallel on machine learning hardware | Physics | 0 | Active |
| US11977963B2 | System and method for INT9 quantization | Physics | 0 | Active |
| US11301247B2 | System and method for handling floating point hardware exception | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.