Memory read masking
US10930327B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jan 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.