Memory array with individually trimmable sense amplifiers
US10930332B2 · kind B2 · utility
0Cited by
357References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.