Apparatuses and methods for selective row refreshes
US10930335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.