Methods for producing nanowire stack GAA device with inner spacer
US10930498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.