Method for forming semiconductor structure
US10930545B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jun 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure is disclosed. Among a stack of mask layers, any other layers above the lowermost thin film layer are subsequently removed to expose the lowermost thin film layer and then the lowermost thin film layer is separately removed by a dry etching process. This improves an etching uniformity of the lowermost thin film layer and ameliorates the issue of material residues. Moreover, thanks to the anisotropic characteristic of the dry etching process, lateral etching of side walls of a trench isolation structure can be mitigated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.