Semiconductor package having recessed adhesive layer between stacked chips
US10930613B2 · kind B2 · utility
1Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jun 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.