Nanowire stack GAA device with inner spacer and methods for producing the same
US10930795B2 · kind B2 · utility
3Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.