Transistor arrangement with a load transistor and a sense transistor
US10931272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Mar 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor arrangement and an electronic circuit with a transistor arrangement are disclosed. The transistor arrangement includes: drift and drain regions arranged in a semiconductor body and connected to a drain node; at least one load transistor cell having a source region integrated in a first active region of the semiconductor body; at least one sense transistor cell having a source region integrated in a second active region of the semiconductor body; a first source node electrically coupled to the source region of the at least one load transistor cell; a second source node electrically coupled to the source region of the at least one sense transistor cell; and a compensation resistor connected between the source region of the at least one sense transistor cell and the second source node. The compensation resistor is integrated in the semiconductor body and has a resistive conductor which includes a doped semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.