High resolution successive approximation register analog to digital converter with factoring and background clock calibration
US10931292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2020 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | May 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.