Patent · US Active

Electrically-verifiable fuses and method of fuse verification

US10935590B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dietrich Bonart · Bad Abbach, DE
Thomas R. Gross · Sinzing, DE
Franziska Haering · Regensburg, DE

Key dates

Filing date	Oct 17, 2017
Grant date	Mar 2, 2021
Priority date	—
Expiry date	Jan 25, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/34
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor wafer includes a semiconductor substrate having a plurality of die areas separated from one another by dicing areas. Each die area includes one or more metal layers above the semiconductor substrate and a plurality of fuse structures formed in at least one of the one or more metal layers. Each fuse structure includes a fuse area between first and second fuse heads. Each die area also includes a first pair of contacts connected to different areas of the first fuse head of at least some of the fuse structures. The wafer can be singulated along the dicing areas into individual dies. A corresponding method of fuse verification is also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.