Synchronization in a multi-tile processing array
US10936008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2018 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Dec 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a computer comprising: a plurality of processing units each having instruction storage holding a local program, an execution unit executing the local program, data storage for holding data; an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by each processing unit; a synchronisation module operable to generate a synchronisation signal to control the computer to switch between a compute phase and an exchange phase, wherein the processing units are configured to execute their local programs according to a common clock, the local programs being such that in the exchange phase at least one processing unit executes a send instruction from its local program to transmit at a transmit time a data packet onto its output set of connection wires, the data packet being destined for at least one recipient processing unit but having no destination identifier, and at a predetermined switch time the recipient process…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.