Instruction chaining
US10936321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is disclosed that that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction into the issue queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.