Error correction of multiple bit errors per codeword
US10936408B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jan 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.