Error correction scheme in flash memory
US10936415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jul 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correction scheme in flash memory. Methods include extending a lifetime of a memory block, including: receiving an indication that an error occurred during a write operation at a first location in a memory block, the first location associated with a faulty page of the memory block; and performing a modified exclusive OR (XOR) scheme on the memory block by: performing a de-XOR operation that generates recovery data of the faulty page; storing the recovery data in a location different from the faulty page of memory; marking the faulty page for exclusion in future de-XOR operations; and performing a parity calculation that generates an updated parity value that includes all pages of the memory block that have been programmed except for the faulty page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.