Methods and systems for verifying out-of-order page fault detection
US10936505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Jan 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Verification of asynchronous page fault in a simulated environment. The methods include providing a simulated environment that includes a simulated processor core, a memory, and an interrupt handler. The methods also include executing a test code in the simulated environment by: executing a non-irritator thread code comprising a plurality of load instructions that span at least two slices of the simulated processor core, executing a first irritator thread code to bias against the execution of the plurality of load instruction by one of the at least two slices of the simulated processor core, and executing a second irritator thread code to invalidate caching of page table entries during execution of the plurality of load instructions in a fast access cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.