David Campbell
33Patents
6h-index
36Co-inventors
69Inventor score
Filing activity: Mar 27, 1979 → Jul 25, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4348157A | Air cooled turbine for a gas turbine engine | Mechanical Engineering; Lighting; Heating | 36 | Expired |
| US4291531A | Gas turbine engine | Emerging Cross-Sectional Technologies | 28 | Expired |
| US4447190A | Fluid pressure control in a gas turbine engine | Emerging Cross-Sectional Technologies | 21 | Expired |
| US10740248B2 | Methods and systems for predicting virtual address | Physics | 10 | Active |
| US10977175B2 | Virtual cache tag renaming for synonym handling | Physics | 10 | Active |
| US10621106B1 | Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) | Physics | 6 | Active |
| US11129454B1 | Electronic assembly for a cover supported by a pole | Human Necessities | 2 | Active |
| US11061810B2 | Virtual cache mechanism for program break point register exception handling | Physics | 2 | Active |
| US5084092A | Method of separating metals from catalyst material | Emerging Cross-Sectional Technologies | 2 | Expired |
| US10649778B1 | Performance optimized congruence class matching for multiple concurrent radix translations | Physics | 1 | Active |
| US11755324B2 | Gather buffer management for unaligned and gather load operations | Physics | 1 | Active |
| US11650926B2 | Virtual cache synonym detection using alias tags | Physics | 1 | Active |
| US11422947B2 | Determining page size via page table cache | Physics | 1 | Active |
| US11221963B2 | Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) | Physics | 1 | Active |
| US10915459B2 | Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes | Physics | 1 | Active |
| US11537519B1 | Marking in-flight requests affected by translation entry invalidation in a data processing system | Physics | 0 | Active |
| US11847064B2 | Buffer and methods for address translations in a processor | Physics | 0 | Active |
| US11086787B2 | Virtual cache synonym detection using alias tags | Physics | 0 | Active |
| US11409663B2 | Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes | Physics | 0 | Active |
| US11210233B2 | System and method for handling address translation invalidations using an address translation invalidation probe | Physics | 0 | Active |
| US11593108B2 | Sharing instruction cache footprint between multiple threads | Physics | 0 | Active |
| US11636043B2 | Sleeping and waking-up address translation that conflicts with translation level of active page table walks | Physics | 0 | Active |
| US12411688B2 | Gather buffer management for unaligned and gather load operations | Physics | 0 | Active |
| US11461474B2 | Process-based virtualization system for executing a secure application process | Physics | 0 | Active |
| US11119945B1 | Context tracking for multiple virtualization layers in a virtually tagged cache | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.