Patent · US Active

Data transfer using a descriptor

US10936517B2 · kind B2 · utility

0Cited by

8References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Norbert Hagspiel · Wissen, DE
Sascha Junghans · Herrenberg, DE
Matthias Klein · Poughkeepsie, US
Joerg Walter · Lörrach, DE

Key dates

Filing date	Jun 25, 2019
Grant date	Mar 2, 2021
Priority date	—
Expiry date	Jul 4, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6042
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.