Inventor · Lörrach, DE

Joerg Walter

22Patents
4h-index
23Co-inventors
63Inventor score

Filing activity: Feb 2, 2000 → Jun 25, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6453450B1 Timing diagram compiler and runtime environment for interactive generation of executable test programs for logic verification Physics 20 Expired
US8117574B2 Implementing a serialization construct within an environment of parallel data flow graphs Physics 6 Active
US10007625B2 Resource allocation by virtual channel management and bus multiplexing Physics 6 Active
US8995210B1 Write and read collision avoidance in single port memory devices Physics 4 Active
US8140315B2 Test bench, method, and computer program product for performing a test case on an integrated circuit Physics 4 Active
US8346527B2 Simulating an operation of a digital circuit Physics 2 Active
US9916268B2 Data transfer using a descriptor Physics 2 Active
US8056037B2 Method for validating logical function and timing behavior of a digital circuit decision Physics 2 Active
US10747625B2 Method for automatically configuring backup client systems and backup server systems in a backup environment Physics 2 Active
US9904616B2 Instruction output dependent on a random number-based selection or non-selection of a special command from a group of commands Physics 1 Active
US9892003B2 Method for automatically configuring backup client systems and backup server systems in a backup environment Physics 1 Active
US9390017B2 Write and read collision avoidance in single port memory devices Physics 1 Active
US9471522B2 Resource allocation by virtual channel management and bus multiplexing Physics 1 Active
US10394733B2 Data transfer using a descriptor Physics 0 Active
US9396116B2 Write and read collision avoidance in single port memory devices Physics 0 Active
US10823782B2 Ensuring completeness of interface signal checking in functional verification Physics 0 Active
US10936517B2 Data transfer using a descriptor Physics 0 Active
US9767048B2 Initializing I/O devices Physics 0 Active
US10830818B2 Ensuring completeness of interface signal checking in functional verification Physics 0 Active
US11163579B2 Instruction generation based on selection or non-selection of a special command Physics 0 Active
US10229035B2 Instruction generation based on selection or non-selection of a special command Physics 0 Active
US9606891B2 Tracing data from an asynchronous interface Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.