Shared decoder circuit and method
US10937477B1 · kind B1 · utility
3Cited by
22References
20Claims
0Family size
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Key dates
| Filing date | Sep 25, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.