Memory device and method of operating the same
US10937503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Oct 16, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.