Semiconductor package and method for manufacturing the same
US10937772B2 · kind B2 · utility
0Cited by
13References
20Claims
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Key dates
| Filing date | May 29, 2019 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes an interconnection structure having a first surface and a second surface opposite to the first surface, a die surrounded by a molding compound over the first surface of the interconnection structure, and a passive device surrounded by a dielectric structure over the second surface of the interconnection structure. The passive device is electrically coupled to the die by the interconnection structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.