Electronic device with a timing adjustment mechanism
US10938395B2 · kind B2 · utility
0Cited by
5References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2020 |
| Grant date | Mar 2, 2021 |
| Priority date | — |
| Expiry date | Mar 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.