Panel to be plated, electroplating process using the same, and chip manufactured from the same
US10941498B2 · kind B2 · utility
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8References
20Claims
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Key dates
| Filing date | Jun 20, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.