Patent · US Active

System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control

US10942851B2 · kind B2 · utility

0Cited by

2References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Wim Heirman · Evergem, BE
Stijn Eyerman · Evergem, BE
Kristof Du Bois · Brüggen, DE
Ibrahim Hur · Portland, US
Joshua B. Fryman · Corvallis, US

Key dates

Filing date	Nov 29, 2018
Grant date	Mar 9, 2021
Priority date	—
Expiry date	Dec 11, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, an apparatus includes a memory access circuit to receive memory access instructions and provide at least some of the memory access instructions to a memory subsystem for execution. The memory access circuit may have a conversion circuit to convert the first memory access instruction to a first subline memory access instruction, e.g., based at least in part on an access history for a first memory access instruction. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.