Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions
US10942985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses relating to performing fast Fourier transform (FFT) configuration and computation operations are described. In one embodiment, a processor includes a matrix operations accelerator circuit that includes a two-dimensional grid of processing element circuits; a first plurality of registers that represents a first two-dimensional matrix coupled to the matrix operations accelerator circuit; a second plurality of registers that represents a second two-dimensional matrix coupled to the matrix operations accelerator circuit; a decoder, of a core coupled to the matrix operations accelerator circuit, to decode a single instruction into a decoded single instruction; and an execution circuit of the core to execute the decoded single instruction to cause the two-dimensional grid of processing element circuits to operate on a first packed data input value and a first complex twiddle factor value to produce a first result and a second result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.