Planar wafer level fan-out of multi-chip modules having different size chips
US10943883B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Sep 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.