Method for forming semiconductor integrated circuit structure
US10943910B2 · kind B2 · utility
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3References
10Claims
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Key dates
| Filing date | Oct 3, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Oct 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.