Method for manufacturing three-dimensional memory structure
US10943916B2 · kind B2 · utility
2Cited by
0References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 2, 2018 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Oct 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a three-dimensional (3D) memory structure and a 3D memory structure are disclosed. A recess is formed on a substrate, a 3D memory component is formed with a bottom in the recess, and then, a peripheral circuit is formed on the substrate outside the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.