Digital alloy based back barrier for P-channel nitride transistors

US10943998B2 · kind B2 · utility

Assignee

• HRL Laboratories, LLC · US

Inventors

• Rongming Chu · Craydon Court, US
• Yu Cao · Craydon Court, US

Key dates

• Filing date: Mar 25, 2020
• Grant date: Mar 9, 2021
• Expiry date: Mar 25, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.