Patent · US Active

Assembling and handling edge interconnect packaging system

US10945335B2 · kind B2 · utility

0Cited by
10References
2Claims
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Key dates

Filing dateNov 20, 2017
Grant dateMar 9, 2021
Priority date
Expiry dateNov 20, 2037

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10T29/49128
  • WIPO fieldAudio-visual technology
  • WIPO sectorElectrical engineering

Abstract

Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.