Processor core supporting a heterogeneous system instruction set architecture
US10949207B2 · kind B2 · utility
1Cited by
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17Claims
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Key dates
| Filing date | Sep 29, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Dec 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/4557
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.