Toby Opferman
23Patents
3h-index
42Co-inventors
59Inventor score
Filing activity: Mar 14, 2005 → Aug 5, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9529708B2 | Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software | Physics | 13 | Active |
| US8171169B2 | Method and apparatus for updating a graphical display in a distributed processing environment | Electricity | 10 | Active |
| US9239801B2 | Systems and methods for preventing unauthorized stack pivoting | Physics | 3 | Active |
| US9535827B2 | RAM disk using non-volatile random access memory | Physics | 2 | Active |
| US11409572B2 | Methods of hardware and software coordinated opt-in to advanced features on hetero ISA platforms | Physics | 1 | Active |
| US8423673B2 | Method and apparatus for updating a graphical display in a distributed processing environment using compression | Physics | 1 | Active |
| US9207940B2 | Robust and high performance instructions for system call | Physics | 1 | Active |
| US9852069B2 | RAM disk using non-volatile random access memory | Physics | 1 | Active |
| US10001953B2 | System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage | Physics | 1 | Active |
| US9524227B2 | Apparatuses and methods for generating a suppressed address trace | Physics | 1 | Active |
| US10949207B2 | Processor core supporting a heterogeneous system instruction set architecture | Physics | 1 | Active |
| US10346167B2 | Apparatuses and methods for generating a suppressed address trace | Physics | 0 | Active |
| US12165686B2 | Memory power management method and apparatus | Physics | 0 | Active |
| US12393427B2 | Core-based speculative page fault list | Physics | 0 | Active |
| US10733108B2 | Physical page tracking for handling overcommitted memory | Physics | 0 | Active |
| US11507368B2 | Spoofing a processor identification instruction | Physics | 0 | Active |
| US11461098B2 | Apparatuses, methods, and systems for instructions for operating system transparent instruction state management of new instructions for application threads | Physics | 0 | Active |
| US11055094B2 | Heterogeneous CPUID spoofing for remote processors | Emerging Cross-Sectional Technologies | 0 | Active |
| US10877751B2 | Spoofing a processor identification instruction | Physics | 0 | Active |
| US11957974B2 | System architecture for cloud gaming | Human Necessities | 0 | Active |
| US11734079B2 | Methods of hardware and software-coordinated opt-in to advanced features on hetero ISA platforms | Physics | 0 | Active |
| US8677022B2 | Method and apparatus for updating a graphical display in a distributed processing environment using compression | Physics | 0 | Active |
| US11989129B2 | Multiple virtual NUMA domains within a single NUMA domain via operating system interface tables | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.