Logical register recovery within a processor
US10949213B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2018 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Apr 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.