Memory interface having data signal path and tag signal path
US10949292B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Oct 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.