Phanindra Kumar Mannava
53Patents
6h-index
67Co-inventors
71Inventor score
Filing activity: May 18, 2001 → Oct 22, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8046488B2 | Dynamically modulating link width | Emerging Cross-Sectional Technologies | 64 | Active |
| US7313712B2 | Link power saving state | Emerging Cross-Sectional Technologies | 49 | Expired |
| US7600080B1 | Avoiding deadlocks in a multiprocessor system | Physics | 19 | Active |
| US7016304B2 | Link level retry scheme | Electricity | 14 | Expired |
| US7610500B2 | Link power saving state | Emerging Cross-Sectional Technologies | 11 | Active |
| US8490107B2 | Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels | Electricity | 8 | Active |
| US7991875B2 | Link level retry scheme | Electricity | 6 | Active |
| US7836144B2 | System and method for a 3-hop cache coherency protocol | Physics | 6 | Active |
| US8473567B2 | Generating a packet including multiple operation codes | Electricity | 5 | Active |
| US11314675B2 | Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols | Physics | 5 | Active |
| US10949292B1 | Memory interface having data signal path and tag signal path | Physics | 3 | Active |
| US7738484B2 | Method, system, and apparatus for system level initialization | Electricity | 3 | Active |
| US8949547B2 | Coherency controller and method for data hazard handling for copending data access requests | Physics | 3 | Active |
| US8468309B2 | Optimized ring protocols and techniques | Physics | 2 | Active |
| US9148485B2 | Reducing packet size in a communication protocol | Electricity | 2 | Active |
| US10042766B1 | Data processing apparatus with snoop request address alignment and snoop response time alignment | Physics | 2 | Active |
| US10324858B2 | Access control | Physics | 2 | Active |
| US10402349B2 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Physics | 2 | Active |
| US11483260B2 | Data processing network with flow compaction for streaming data transfer | Physics | 1 | Active |
| US7320094B2 | Retraining derived clock receivers | Electricity | 1 | Expired |
| US9372798B2 | Data processing apparatus having first and second protocol domains, and method for the data processing apparatus | Physics | 1 | Active |
| US10970225B1 | Apparatus and method for handling cache maintenance operations | Physics | 1 | Active |
| US7831776B2 | Dynamic allocation of home coherency engine tracker resources in link based computing system | Physics | 1 | Active |
| US8898393B2 | Optimized ring protocols and techniques | Physics | 1 | Active |
| US8606934B2 | Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.