Semiconductor device
US10950541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Mar 16, 2021 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.